Intel has showcased its packaging prowess with multi-chiplet products featuring 18A/14A node tiles, Foveros 3D & EMIB-T technology.
Intel Is Really Going Big With Next Generation 18A/14A Process Nodes, Foveros 3D Technology & EMIB-T: Featuring Conceptual & Highly Scalable Design With Up To 16 Compute Tiles, 24 HBM Sites & More
Intel isn’t resting on its advanced packaging solutions and has just demonstrated the future for customers looking to leverage its technology in making the chips of the future.
This technology will become the standard for next-generation chips for HPC, AI, Data Centers, and more. Intel Advanced Packaging Solutions will also increase competition against TSMC’s CoWoS solution, which has also outlined a 9.5 Reticle solution utilizing the A16 process node and more than 12 HBM4E (CoWoS-L) units.
The following are some of the key technologies that Intel will leverage to produce the next generation of computing powerhouses:
- Intel 14A-E: Breakthrough logic with RibbonFET 2 and PowerDirect.
- Intel 18A-PT: Back-end power-first, improving logic density and power reliability.
- High Performance Upper Die: Next generation performance with increased density and performance per watt (Intel 14A/14A-E Process Node).
- 3D Live Foveros: Precise 3D stacking with hybrid bonding in ultra-fine tones.
- EMIB-T (Embedded Multi-die Interconnect Bridge): Next generation EMIBs add TSVs for higher bandwidth and greater tile integration.
- HBM Protocol Support: Seamless support for the latest and future HBM standards (HBM4/HBM5/HBM-Next).
- >12x Reticle Scalability: It is possible for the architecture to go beyond the limits of the traditional reticle.
In a video published by Intel, the company showcases two advanced packaging chip solutions. This is definitely a conceptual design, but the design is the interesting part. One chip was showcased with four compute tiles and 12 HBM sites, while the second chip featured 16 compute tiles with 24 HBM sites. There are also twice as many LPDDR5X controllers, with up to 48 on the larger solution.

This chip consists of a computing base die that utilizes 18A-PT process technology. These tiles house SRAM, similar to how Clearwater Forest is built. Clearwater Forest is built on the 18A process node and hosts 576 MB of L3 cache on its triple Base Tile solution. The base tile for Clearwater Forest is made with Intel 3 process technology, so we can expect Intel 18A-PT to further optimize & increase the amount of SRAM we see in future chips.

The base tile then ends with the main computing tile, which can include AI Engines, CPUs, or other IP. It is manufactured on Intel 14A or 14A-E process technology, and connected to the base tile using Foveros 3D packaging solution. It acts as a 3D stack.

Several chiplets are then connected and further connected to the memory solution using the EMIB-T interconnect. The top chips that have been visualized use 24 HBM sites, and these can be either modern HBM standards, such as HBM3/HBM3E, or future standards such as HBM4/HBM4E or HBM5. This single package can also accommodate up to 48 LPDDR5x controllers to truly expand memory density for AI and data center workloads.

Intel also stated that it has a wide-ranging ecosystem engagement plan and is engaging directly with industry partners to accelerate time to market and supply chain resiliency.

This showcase of advanced packaging chips is clearly aimed at external customers looking for what Intel has to offer, and especially what the 14A has to offer, as the node is designed specifically for third-party customers. Intel has stated that the 18A is mostly used for its own internal products, but with the 14A, they have more customers engaging with them, and with advanced packaging solutions like the ones highlighted here, Intel seems to be in for a big game.
The only thing we have to see now are actual products and confirmation regarding which products and which major players will be able to use Intel Fabs. There are a few hints here and there, but nothing conclusive yet. We have to remember that Intel has been at the top of the advanced packaging game for some time. Their final chip, the Ponte Vecchio, was a marvel from an engineering standpoint, but due to numerous delays related to results, the product was not very successful, and several Intel projects, including Falcon Shores, were cancelled.



The company is back with its highly anticipated Jaguar Shores and Crescent Island GPUs for AI, but at the same time, their real test now will be getting deals from third parties, as many are leveraging the company’s 14A technology.
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