Samsung Electronics VP Says ‘Process Miniaturization Alone Can Only Yield 10-15% Improvement’ Emphasizes Need to Explore New Approaches

The 2nm GAA process offers significant performance and efficiency improvements over Samsung’s older manufacturing process, but the company’s Vice President of Foundry said that node shrinkage offers only small benefits and believes there is a need to look for alternatives. To this end, the Korean tech giant has proposed the ‘Design and Process Integration Optimization’ (DTCO) method, which examines modifications that can be implemented to enhance the power of cutting-edge nodes.

One area Samsung has improved is the transition from FinFET to GAA structures, maximizing current control capabilities, and allowing the 2nm node to introduce a number of significant improvements.

Speaking at the eighth Semiconductor Research-Academy-Industry Exchange Workshop held at COEX in Samseong-dong, Seoul, Samsung Electronics Foundry Vice President Shin Jong-shin said that while the industry has turned to DTCO, both the company and rival TSMC have dedicated teams pursuing design and process improvements.

“Now, process miniaturization alone can only deliver 10-15% improvements. As process performance improvements reach their limits, the industry is paying attention to DTCO. At 7nm, about 10% of the overall performance improvement is attributable to DTCO. We estimate that share will reach 50% at 3nm and below. Both Samsung and TSMC have dedicated DTCO teams and are working on simultaneous design and process improvements.”

According to The Elec, at DTCO, engineers review existing process constraints while looking for alternatives based on designers’ requests, such as Tesla. By modifying this process, cells can be placed more efficiently, and surface area can be reduced. Samsung has used the FinFET architecture in previous iterations and has switched to a Gate-All-Around (GAA) structure, starting with the 3nm variant, which did not produce sufficient results, but the 2nm node shows a lot of promise.

“When moving from N nodes to M nodes, the performance increase is about 15%, and the area reduction is also about 15%. In contrast to the field of artificial intelligence (AI) where performance doubles every few months, in the world of semiconductor processing, even a 1-2% difference is very important. A 1-2% performance difference can be a process selection criterion.”

In addition to exploring other alternatives, Samsung is also leveraging AI in an effort to automatically create new cell structures that can cover smaller areas and reduce power consumption. Samsung Electronics Foundry executives said that DTCO will expand its development by developing System-Process Co-Optimization (SPCO) and System-Design-Process Co-Optimization (SDTCO), which will further refine this process.

Samsung has reportedly completed the basic design of its second generation 2nm GAA process, with its third iteration SF2P+ expected to be implemented within two years. It’s possible that the Korean foundry has ventured deep into DTCO to develop a better variation of its 2nm GAA process, which is why they may be delaying the 1.4nm node in favor of improving the current process rather than competing directly with TSMC.

News Source: The Elec

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