Intel Diamond Rapids “Xeon” CPUs Will Feature Separate CBB “Core Building Block” Tiles and IMH “I/O + Integrated Memory Hub” Tiles

The next generation of Intel Diamond Rapids “Xeon” CPUs will carry two new and separate tiles codenamed CBB and IMH.

Intel Diamond Rapids “Xeon” CPU Equipped with CBB Compute and IMH I/O+IMC Tiles, Also Supports PCIe Gen6

New details of the next generation Intel Diamond Rapids “Xeon” CPUs have been spotted in a Kernel patch. This patch reveals the design philosophy of Intel’s upcoming Xeon architecture and how the chips will be built.

For Diamond Rapids, Intel will introduce two new tiles. First, we have the CBB “Core Building Blocks” that will be the compute tiles, and the key detail is that, unlike Granite Rapids, which adds IMC on the same tile, Diamond Rapids will separate them.

The IMC or integrated memory controller will be displayed on the new “Integrated I/O & Memory Hub” IMH tile. This is separate from the computational tile (CBB), and Diamond Rapids is said to feature up to two of these IMH prints. @InstLatX64 also suggested that the IMH print would be placed on the base tile, similar to how Clearwater Forest does things.

Similar to Intel Sapphire Rapids, Diamond Rapids relies on discovery tables for uncore enumeration. Key differences and additions include:

• The DMR may have two Integrated I/O and Memory Hub (IMH) die, which are separate from the compute tile die (CBB). Each CBB mold and IMH mold has its own discovery table.
• Unlike previous CPUs that took the global discovery table portal exclusively via PCI or MSR, DMR uses PCI for IMH PMON discovery and MSR for CBB PMON discovery
• DMR introduces several new PMON types, including SCA, HAMVF, D2D_ULA, UBR, PCIE4, CRS, CPC, ITC, OTC, CMS, and PCIE6.
• Unlike SPR, the IIO-free counter in DMR is MMIO-based.

via Kernel.org